Tektronix TLA7M3-optSTD 102ch Logic Analyzer Module
JPY120,000 1stock

Form Factor Module (proprietary interface/bus)
Number of Channels 34 ch
Maximum Conventional Timing Rate 250 MHz
Maximum Transitional Timing Rate 250 MHz
Maximum Glitch Timing Rate 100 MHz
Memory Depth/Channel-Normal 32 KB
Channel to Channel Delay 1 ns
Minimum Recognizable Glitch Width 2 ns
Setup/Hold Time 2.0 ns
Maximum Trigger Sequence Levels 16 Levels
Maximum Trigger Sequencing Rate 250 MHz
No of Pattern Recognizers 16 QTY
No of Range Recognizers 4 QTY
No of Counter Timers 2 QTY
Input Capacitance 2 pF

OPT STD:2GHz Timing 200MHz State,512KDEPTH